Re: [pci] about synthesis

["Jeremy Fillingim" <jfilling@aros.net>]

What you put in your constraint files depends a lot on what toolset you are
using and what your target application is.

For example, I am using the Insight Electronics PCI 200 Development Kit
(Xilinx Spartan-2 200k -5), and the OpenCore PCI core as a guest bridge.  My
synthesis tool is the Xilinx WebPack (which supports up to 300k gate parts,
and is free $$$).

In the documentation for the kit, they have a list of which FPGA pins are
attached to the PCI connector.  So my UCF (User Constraint File) contains
the mapping from FPGA pins to PCI Board signals.  These are really the only
constraints you should need, as the PCI core meets 33 MHz timing very
easily.  You can always add constraints to the PCI clock and Wishbone clock,
but in my experience they were not neccessary.

However, if you have added some additional logic on the Wishbone bus, you
may or may not need to constrain some of your own logic signals to ensure
that the design meets your timing requirements.

Hope this helps.  Good luck.

----- Original Message -----
From: <random_user@163.com>
To: <pci@opencores.org>
Sent: Monday, September 23, 2002 8:52 AM
Subject: [pci] about synthesis


> hi all,
>       I am trying to synthesize the project,but I don't know what I should
> write in the constraints file .
>       Could someone tell me ? Thx!
>
> regards,
> wangc
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