Re: [pci] False PERR error at wait_perr4 (race?)

["Miha Dolenc" <mihad@opencores.org>]

Hi!

You are absolutely right. It's a race and it was reported before by other
members. And it has also been repaired already - please checkout system.v in
bench/verilog again to fix it. The fix hasn't been tested on ModelSim yet,
so feedback would be appreciated.

Regards,
Miha Dolenc

----- Original Message -----
From: <pinhas.krengel@formalized.com>
To: <pci@opencores.org>
Sent: Sunday, April 14, 2002 9:20 PM
Subject: [pci] False PERR error at wait_perr4 (race?)


> The message in the log file of pci_tb.log is:
> **********************************************************
>  At time            113280000
>  Test BRIDGE'S RESPONSE TO PARITY ERRORS DURING MASTER READS
>  *FAILED* because
>   PCI bridge failed to assert invalid PERR on Master Read reference!
> **********************************************************
>
> I checked in the waves and verified that the PERR is asserted at the right
time. The test that fails is at begin:wait_perr4. perr_asserted is never
asserted (to 1), because the porcess is disabled after two cycles:
>         repeat(2)
>             @(posedge pci_clock) ;
>
>         //by PK debug
>         $display("%d disable wait_perr4", $time);
>         disable wait_perr4 ;
>
> I need still to check but, it seems that two cycles is okay and the reason
for not working on model sim is race.
>
> My question:
> Did somebody try to work with model-sim or verilog XL. If yes what are the
observations.
>
>
> --
> Best Regards,
>
> Pinhas Krengel
> Sr. ASIC / FPGA Engineer
> Formalized Design Alliance Partner
> 011 972-9-894-7865 Home Office
> 011 972-54-679-119 Portable
> 480-545-4555 Jim McHood, VP Engineering
> www.formalized.com
>
> --
>
>
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