Re: [pci] PCI target

[Duane Clark <dclark@akamail.com>]

MikeJ wrote:

> Tadej & people,
> 
> Still alive !
> 
>  
> 
> Sorry things have been quiet this month - I've been away longer than 
> expected and have just got home.
> 
> I have built a (prototype & simple - dummy backend i/f) virtex 300e-5 
> pci target which meets my draft 33mhz timespecs.
> 
> However for faster speeds I strongly suspect I am going to have to use 
> virtex specific cells which would have to be rloc'd.
> 
> What are the general feelings about introducing vendor specific versions ?


I just want to make sure that you are aware of the "PCILOGIC" special 
block that is on the virtex/spartan II devices. It is designed for the 
IRDY/TRDY signal handshaking, to allow you to meet the stringent timing 
requirements, especially when you get to doing a bus master.

I personally think that making a completely generic VHDL design for 
FPGAs is going to be extremely difficult.

Duane




--
To unsubscribe from pci mailing list please visit http://www.opencores.org/mailinglists.shtml