Re: [openrisc] WB:RISC Clock Ratios

["Damjan Lampret" <lampret@opencores.org>]

----- Original Message -----
From: "Brian Adams" <brian.adams@annapmicro.com>
To: <openrisc@opencores.org>
Sent: Wednesday, June 25, 2003 8:51 AM
Subject: [openrisc] WB:RISC Clock Ratios


> Hello All,
>
>   I have a (hopefully) quick sanity check to ask. For the SOC we are
> designing we want to have the ability to run WB:RISC clock ratios of 1:1
> or 1:2.  To do this I would have to (?)
>
> 1) Define OR1200_CLKDIV_2_SUPPORTED
> 2) Drive clmode_i on or1200_top appropriately (we plan to use an
> external switch or jumper)
> 3) Drive iwb_clk_i and dwb_clk_i with either the full or half rate WB
> clock (depending on how we set #2)

Exactly right.

>
>   Also, are there restrictions on the 1:2 WB/RISC clock relationships?
> ie. Must the WB clock must be EXACTLY 1/2 the RISC clock, and phase
> aligned.  We plan to have both, but I was wondering if either was
> absolutely necessary.

It needs to be phase aligned because there is no logic to combat
metastability if clocks are not in sync. There can be skew between main
clock and 1/2 clock, but this simply means reduction in max clock frequency
(you STA will tell you that). But yes the clocks need to be in sync.

>
>  I it appears that OR1200_CLKDIV_2_SUPPORTED, OR1200_CLKDIV_4_SUPPORTED
> and clmode were added to make it easy to do just what I have proposed,
> but I have been wrong before. =)

You are right this time. =)

regards,
Damjan

>
> Thanks,
> Brian
>
>
>
>
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