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[openrisc] about cache scheme

To: "openrisc@opencores.org" <openrisc@opencores.org>
Subject: [openrisc] about cache scheme
From: "zhustudio" <zhustudio@ict.ac.cn>
Date: Thu, 26 Jun 2003 9:31:40 +0800
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org

hi all,

i have find if you enable cache in compile stage, and then sim in or1200 soc platform, the instruction cache is enabled between 63400ns, and the instruction is l.mtspr r0,r10,0x11,  diassemble is 0xc0005011. i have test many programs that are provided in sw directory. so can anyone tell me why perform this sheme? is it a program compiler option or others. thank you

Jiahui Zhu

Email: zhustudio@ict.ac.cn
Date: 2003-06-26



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