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[openrisc] OR1200 update, ORP update



Hi Folks,

OR1200 has been updated. Most updates fix warnings in Synplicity synthesis tools. There are also some timing optimizations, mem2reg now uses generic implementation which is faster. Default multiplier in ASIC configuration is the generic one. The most important optimization is related to cache controllers.

I still have more optimizations and these will come in the CVS next week.

Another thing that has been added is the orp_soc and xess directories. These contain generic OpenRISC Reference Platform SoC and environment for the XESS XSV800 board. These directories are right now under heavy modification. So far there is an environment that can be synthesized for XSV800 and a ORP monitor software (this will also be updated very soon). I'll make a post with detailed instructions how to use the orp_soc and xess environments. Until then, I have attached my post to the XESS forum.

regards,
Damjan

Post to the XESS forum:

Hello!

Is somebody interested to play with a 32-bit RISC on your XSV800 
board? Want to see if your UART works? Want to see how to interface
to XSV on-board UART/Audio/VGA/PS2/SRAM/Flash/Ethernet devices?

Then you might want to try OpenCores' test application for XESS 
XSV800 board. Right now only parts of it are in OpenCores CVS and
there is no instructions how to use the test application on the web, 
but I thought you might be interested to know in advance and wait
for other parts to be available.

Right now you can get the complete RTL (Verilog, and yes, completely 
FREE including for commercial projects !) and synthesis
project file for Synplify 7 and constraint file for Xilinx Foundation 
ISE 4.1. In case you don't have the same synthesis env. or don't have 
the time to deal with the synthesis/P&R, you can also get the .exo 
and .svf files for direct download.
Also available is the orp monitor 'C' sources (the one that is merged 
in the .exo file) and complete OpenRISC development tools. Soon to be 
available is uClinux (it is already running on OpenRISC !).

Right now not all peripherals are fully fucntional. Audio for example 
is broken (we are changing it right now) and VGA has problems 
connecting to VGA connector because we use Right SRAM bank. Ethernet 
needs 25MHz clock.
We expect to fix this issues in the following days/weeks (depends if 
we get beta testers and developers). Remember OpenRISC team is doing 
this in free/spare/hobby time ! Also it would help if we would have 
more XSV800 boards (a hint to XESS ;-) ...

Anyway if you are interested, start by first reading this:
http://www.opencores.org/cvsweb.shtml/or1k/xess/xsv_fpga/README 
(click on Download link)

Once you have read the READMe, you can download the whole test 
application sources by clicking this:
http://www.opencores.org/cgi-bin/cvsget.cgi/or1k/xess/xsv_fpga/README

or download only the .exo and .svf files:
http://www.opencores.org/cgi-bin/cvsget.cgi/or1k/xess/xsv_fpga/

If you want to browse sources online, go here:
http://www.opencores.org/cvsweb.shtml/or1k/xess/xsv_fpga/

*** IMPORTANT: OpenRISC team is hoping to get beta testers and/or new 
SW/HW developers willing to help us in our mission. For example we 
need a tutorial document how use this test app with XSV board ... ***

regards,
Damjan

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