[openrisc] three more problems

[jimmy87@sunplus.com.tw]

Hi Damjan,
I want to pose another two problems about OR1K.

1. if exception such as overflow(add), divided by zero(div/mod) happens in the
    delay slot, then we must let CPU keep one bit like MIPS to show the
exception
    is in the delay slot.
    What do you wanna handle it?

2. it seems that external interrupt enable control registers are not defined
yet.
3. I don't know if you think the follow suggestions are feasible and should be
done.
    (*). if no MMU, I feel we should define one simple memory architecture.
            Such as one region is uncached/kernel mode and one region is
cached/user mode.
             one region is cached/kernel mode.


Best regards, Jimmy