[ethmac] ethernet core information

["Rodrigo Sosa" <sosa_rodrigo@hotmail.com>]

Hi!,
I'm writing to you because I´m trying to implement the ethernet core into an 
FPGA.
I have a board with a Virtex FPGA and a Ethernet Phy Transceiver.

I have read the ip core document, but there is something that i'm not used 
to.
The wishbone interface......
Should I have and extra module to control the ip core, or it should work 
like an stand alone design?

Maybe it  is a silly question,  but I just want to know if I have to design 
a kind of control module compatible with the wishbone interface.

Do you have something developed (ethernet cores) in VHDL ?


Thank you

=================OOOO====================

          Rodrigo Sosa Lopez
   Universidad de las Americas Puebla
    Ing. Electronica y Comunicaciones
  e-mail: sosa_rodrigo@hotmail.com




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