[ecc] Re:

[DianTN <diantn@yahoo.com>]

If I see your code, I think there will be a 'hazard' such as "double
driver". Especially when sel_a and sel_b are both high, y will be
driven by two different signals. Actually, this is the purpose of the
'nested if' structure, it places a logic gate between the signals and
y.


Because of this reason, I also suggest to change the structure. I'm
sorry.

Regards,


Dian.

--- zhu.xiangyang@mail.zte.com.cn wrote:
> 
> 
> Hello everyone:
>     I am a new comer to this mailinglist(so i have no any
> contribution to
> opencore :( ).
> Because i have been engaged in IC design only for a short time,
> there are some
> question
> puzzling me. I am using Verilog HDL. During my coding someone
> inspected my code
> and told
> me there are probably some problems in my code.
>     My code is illustrated as follows:
> 
>  module(clk, reset, y, a, b, sel_a, sel_b);
>    input clk, reset, a, b, sel_a, sel_b;
>    output y;
>    reg y;
>    always@(posedge clk or negedge reset)
>      begin
>      if(reset)
>        y <= 0;
>       else
>         begin
>     //////////////
>         if(sel_a)
>           y <= a;
>         if(sel_b)
>           y <= b;
>     /////////////
>         end
>      end
>  endmodule
> 
> The inspector told me i should do as below:
>  ////////////
>      if(sel_b)
>        y <= b;
>      else if(sel_a)
>        y <= a;
>  ////////////
> He said if i do as i like pre-synthesis simulation and
> post-synthesis
> may be diffenent, because different synthesis tools may interpret
> it
> differently. He demanded me to change my code. If i have to change
> my
> code it will be a disaster, because i  have writen about 4,000
> lines
> of code using the same structer.
> 
> Must i change my code? Please help me.
> 
> 


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