CVSROOT: /home/oc/cvs Module name: or1k Changes by: lampret 02/03/29 17:31:31 Modified files: xess/xsv_fpga/orp_soc/rtl/verilog/audio: fifo_empty_16.v Log message: Added synthesis off/on for timescale.v included file. -- To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml