[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[cvs-checkins] MiniUART/rtl/vhdl Txunit.vhd

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] MiniUART/rtl/vhdl Txunit.vhd
From: OpenCores CVS Agent <cvs-checkins-agent@opencores.org>
Date: Mon, 25 Mar 2002 21:18:35 +0100
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	MiniUART
Changes by:	philippe	02/03/25 21:18:35

Modified files:
	rtl/vhdl       : Txunit.vhd 

Log message:
	Corrected bug on LoadA signal in Txunit.vhd.
	Load signal is now correctly sampled by BR_CLK.

--
To unsubscribe from cvs-checkins mailing list please visit http://www.opencores.org/mailinglists.shtml

Prev by Date: [cvs-checkins] ethernet/rtl/verilog eth_wishbone.v
Next by Date: [cvs-checkins] MiniUART/rtl/vhdl Rxunit.vhd
Prev by thread: [cvs-checkins] MiniUART/rtl/vhdl Rxunit.vhd
Next by thread: [cvs-checkins] ethernet/rtl/verilog eth_top.v
Index(es):
- Date
- Thread