[cvs-checkins] uart16550/rtl/verilog uart_wb.v

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	uart16550
Changes by:	gorban	02/02/07 17:20:28

Modified files:
	rtl/verilog    : uart_wb.v 

Log message:
	major bug in 32-bit mode that prevented register access fixed.

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