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[cvs-checkins] ethernet/rtl/verilog eth_defines.v eth_wishbon ...

CVSROOT:	/home/oc/cvs
Module name:	ethernet
Changes by:	mohor	02/02/05 17:44:46

Modified files:
	rtl/verilog    : eth_defines.v eth_wishbone.v 
Added files:
	rtl/verilog    : eth_fifo.v 

Log message:
	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
	MHz. Statuses, overrun, control frame transmission and reception still  need
	to be fixed.

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