[cvs-checkins] pci/ pps/crt/rtl/verilog/ssvga_defines.v pps/c ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	mihad	02/02/01 16:25:14

Modified files:
	apps/crt/rtl/verilog: ssvga_defines.v ssvga_fifo.v ssvga_top.v 
	                      ssvga_wbm_if.v ssvga_wbs_if.v top.v 
	apps/crt/syn/exc: pci_crt.exc 
	apps/crt/syn/out/bit: pci_crt.bit 
	apps/crt/syn/out/sdf: crt_time_sim.sdf 
	apps/crt/syn/out/verilog: crt_time_sim.v.bak 
	apps/crt/syn/ucf: pci_crt.ucf 
	apps/sw/driver : Makefile README.txt sdram_test.c slide.c 
	                 spartan_drv.c spartan_kint.h 
	apps/sw/driver/fb: Makefile XF86Config-fb spartan_fb.c 
	                   spartan_kint.h startx 
	old_stuff/Decoder: readme.txt 
	old_stuff/delayed_sync: READ_ME.txt 
	old_stuff/driver: Makefile README.txt sdram_test.c slide.c 
	                  spartan_drv.c spartan_kint.h 
	old_stuff/driver/fb: Makefile XF86Config-fb spartan_fb.c 
	                     spartan_kint.h startx 
	old_stuff/wb_slave: READ_ME.txt 
	old_stuff/wb_slave/test_bench: READ_ME.txt 
	rtl/verilog    : bus_commands.v cbe_en_crit.v 
	                 conf_cyc_addr_dec.v conf_space.v cur_out_reg.v 
	                 decoder.v delayed_sync.v delayed_write_reg.v 
	                 fifo_control.v frame_crit.v frame_en_crit.v 
	                 frame_load_crit.v irdy_out_crit.v 
	                 mas_ad_en_crit.v mas_ch_state_crit.v out_reg.v 
	                 par_crit.v pci_bridge32.v pci_decoder.v 
	                 pci_in_reg.v pci_io_mux.v pci_master32_sm.v 
	                 pci_master32_sm_if.v pci_parity_check.v 
	                 pci_target32_clk_en.v pci_target32_devs_crit.v 
	                 pci_target32_interface.v pci_target32_sm.v 
	                 pci_target32_stop_crit.v 
	                 pci_target32_trdy_crit.v pci_target_unit.v 
	                 pciw_fifo_control.v pciw_pcir_fifos.v 
	                 perr_crit.v perr_en_crit.v serr_crit.v 
	                 serr_en_crit.v synchronizer_flop.v timescale.v 
	                 top.v wb_addr_mux.v wb_master.v wb_slave.v 
	                 wb_slave_unit.v wbr_fifo_control.v 
	                 wbw_fifo_control.v wbw_wbr_fifos.v 

Log message:
	Repaired a few bugs, updated specification, added test bench files and design document

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