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[cvs-checkins] mem_ctrl/ est_bench/sync_cs_dev.v est_bench/te ...
CVSROOT: /home/oc/cvs
Module name: mem_ctrl
Changes by: rudi 01/07/29 09:55:58
Removed files:
test_bench : sync_cs_dev.v test_bench_top.v test_lib.v
tests.v wb_mast_model.v wb_model_defines.v
test_bench/160b3ver: DP160B3B_RU.V adv_bb.v dp160b3b.v
dp160b3t.v f160b3b.bkb f160b3b.bke
f160b3b.bkt f160b3t.bkb f160b3t.bke
f160b3t.bkt read.me t160b3b.v t160b3t.v
test_bench/sdram_models/16Mx16: mt48lc16m16a2.v
mt48lc16m16a2.zip test.do test.v
wave.do
test_bench/sdram_models/16Mx8: mt48lc16m8a2.v test.do test.v
wave.do
test_bench/sdram_models/2Mx32: bank0.txt bank1.txt bank2.txt
bank3.txt mt48lc2m32b2.v test.do
test.v wave.do
test_bench/sdram_models/32Mx8: mt48lc32m8a2.v test.do test.v
wave.do
test_bench/sdram_models/4Mx16: bank0.txt bank1.txt bank2.txt
bank3.txt mt48lc4m16a2.v test.v
test_bench/sdram_models/4Mx32: mt48lc4m32b2.v test.do test.v
wave.do
test_bench/sdram_models/8Mx16: mt48lc8m16a2.v test.do test.v
wave.do
test_bench/sdram_models/8Mx8: bank0.txt bank1.txt bank2.txt
bank3.txt mt48lc8m8a2.v test.v
test_bench/sram_models/IDT71T67802: idt71t67802s133.v
idt71t67802s150.v
idt71t67802s166.v
idt_512Kx18_PBSRAM_test.v
readme_71T67802
test_bench/sram_models/MicronSRAM: mt58l1my18d.v output.txt
test.do test.v wave.do
verilog : mc_adr_sel.v mc_cs_rf.v mc_defines.v mc_dp.v
mc_incn_r.v mc_mem_if.v mc_obct.v mc_obct_top.v
mc_rd_fifo.v mc_refresh.v mc_rf.v mc_timing.v
mc_top.v mc_wb_if.v
Log message:
- Changed Directory Structure ...
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