[cvs-checkins] mem_ctrl/verilog mc_cs_rf.v mc_defines.v mc_dp ...

[OpenCores CVS Agent <cvs-checkins-agent@opencores.org>]

CVSROOT:	/home/oc/cvs
Module name:	mem_ctrl
Changes by:	rudi	01/06/03 13:37:17

Modified files:
	verilog        : mc_cs_rf.v mc_defines.v mc_dp.v mc_mem_if.v 
	                 mc_obct.v mc_refresh.v mc_rf.v mc_timing.v 
	                 mc_top.v mc_wb_if.v 

Log message:
	1) Fixed Chip Select Mask Register
	- Power On Value is now all ones
	- Comparison Logic is now correct
	
	2) All resets are now asynchronous
	
	3) Converted Power On Delay to an configurable item
	
	4) Added reset to Chip Select Output Registers
	
	5) Forcing all outputs to Hi-Z state during reset