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Re: [oc] Synchron Moore State Machine

> So it is better to have a (synchronous) generated signal to generate a
> switch condition for your state machine, the easiest solution is to define
> a single signal with reset value '0' and first clock transition to '1'.

Or use a synchronous reset for your statemachines. Altera HDL (AHDL) always 
uses a synchronous reset when it generates statemachines from tables. Maybe a 
hidden hint from Altera ???

Richard

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