[oc] How can I wrap ASB with AHB efficiently?

[ynwie@iris.snu.ac.kr]

Hi, My name is Sungchan Kim.

I'm a graduate stduent from Korea.

My research theme is about an optimization of communication 
architecture in SoC.

Currently I'm making a ASB2AHB wrapper. One of most difficult thing is

ASB use both rising and falling clock edge but AHB use rising edge only.

I use ASB clock with AHB's inverted at same clock period.

The problem is following.

At falling edge of ASB(rising edge of AHB), ASB master release valid 
adress on the address bus,

and util next rising edge, bus slave or decoder should response to the 
transaction such as DONE, WAIT and so on.

But according to AHB spec, response may valid until next rising edge of 
clock.

That's a problem which is bothering me :-(

I synthesized my vhdl code with VIRTEX II library, maximum clock speed 
was about 80MHz. 

However, BWAIT signla in ASB must be valid rising edge of ASB clock 
following falling edge which release valid address.

So actual operating clock frequency is twice of a result of synthesize.

How can I solve this problem?

I'd like to ask for your excuse for posting such kind of quention here. :-)

But the help of experts here is really needed.

Thanks in advance.

from Sungchan Kim.
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