Re: [oc] Volunteer for GPL'd CAD tool

["Marko Mlinar" <markom@opencores.org>]

Just a few thoughts...

> > Proprietary CAD tools have the usual inconvenience of proprietary
> > software. They are impossible to debug for the end user, the
> > interfaces and file formats are not unified, each manufacturer
> > redesigns its own place and route algorithms... It is obviously a
> > stupid waste of time and intellectual effort.
>
> That's probably true. However all C/C++ compiler team implements the same
> optimization algorithms. That's also a 'stupid waste of time and
> intellectual effort'. Even when GCC is there for more than a decade... I
> don't think you could change that.
This is not a waste of intellectual effort. Intel has its own compiler
for its cpus, yet I don't know anyone using it.
Just like cpu-compiler, FPGA-PAR SW is undividable.
So even if Xilinx would not be successful selling their PAR SW,
they would have to develop it to continue developing their chips.

> Hmmm... I would say, the idea is great. But! I would give everyone the
> opportunity to implement their own back-end without joining the open
effort.
> I mean: Xilinx would probably still maintain it's own PAR (back-end in
your
> words) but if it would be compatible with your front-end the world would
be
> much nicer already. So I'dd suggest creating an open and detailed
> specification of the interface between the front-end and the back-end, and
> leave the choice open to use any front-end with any back-end. And once
> again: isn't EDIF something like that already?
Xilinx has a lot of patents on FPGAs. Maybe some of them cover also SW?

Marko


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