Re: [oc] Volunteer for GPL'd CAD tool

[nico <nicolas.boulay@ifrance.com>]

No need to open FPGA format. You could generate direct VHDL cell
interconnection and then used the xilinx place&route tools. I beleive
that Synchronicity work that way with Xilinx and Altera.

The hard stuff come to transforme HDL to gate level.

nicO


bad_boy1980@thaimail.com a écrit :
> 
> ----- Original Message -----
> From: MoT <Sebastien.Villemot@e... >
> To: cores@o...
> Date: Fri, 3 Mar 2000 17:18:42 +0100 (CET)
> Subject: [oc] Volunteer for GPL'd CAD tool
> 
> >
> >
> > Hi folks !
> >
> > First I'd like to congratulate you for yor job. Making open
> > hardware is
> > obviously a great idea and I hope it will have the same success
> > than open
> > software.
> >
> > I'm a graduate level student in theoretical computer science ; I
> > also
> > have good programming experience (asms/C/C++/Java), and some
> > hardware
> > design experience (though it was not with VHDL, I can learn it).
> >
> > I've some ideas of things for which I could help, but first I'd
> > like to
> > let you know about a problem that concerns me.
> >
> > I feel really frustrated of the fact that it is impossible to do
> > the whole
> > design of a core under my favourite development plateform, namely
> > GNU/Linux :) There are some GPL'd VHDL simulation tools (Savant,
> > which
> > seems almost usable, and FreeHDL which is under heavy development).
> > However it is impossible to actually produce a netlist, do the
> > placement
> > and routing phase, and generate the configuration bitstream of my
> > target
> > FPGA. The only solution to do so is to buy proprietary CAD software
> > and to
> > run it on Microsoft's proprietary OS.
> >
> > The main raison for this situation is the fact that FPGA
> > manufacturers do
> > not provide full technical information about their chips (let me
> > know if
> > I'm wrong, maybe I'm missing something). For example, Xilinx
> > provide a
> > "Virtex Series Configuration Architecture User Guide" for their
> > Virtex
> > chips, which explains parts of the configuration bitstream for
> > logical
> > units, but there is no information about how to actually configure
> > routing
> > between CLBs and IOBs.
> >
> > Of course, not providing these informations is a deliberate choice;
> > designers wanting to use FPGAs have no other solution than buying
> > the
> > proprietary CAD software of the chip manufacturer. And in the same
> > state
> > of mind, manufacturers do not provide any Linux support because it
> > doesn't
> > seem worth; it is a well known fact that Linux is a closed
> > environment
> > only used by hackers and mad students :)
> >
> > Apart from the fact that designers must set up a Windows box, there
> > are
> > some other negative consequences of this situation. For example, I
> > worked
> > with computer science researchers who developped a new HDL (it is
> > called
> > Jazz, available on http://www.cma.ensmp.fr/jazz/). It can describe
> > synchronous digital circuits, and has some very interesting
> > features not
> > found in other HDLs. But to actually run a design in a FPGA with
> > this HDL,
> > we had to do ugly hacks, create our own tools to convert the
> > netlist
> > produced by jazz to the input format of the xilinx tools. The tool
> > chain
> > becomes far bigger and more complex than it should be; moreover,
> > the
> > different tools run on different hardware platforms, which is very
> > annoying.
> >
> > Proprietary CAD tools have the usual inconvenients of proprietary
> > software. They are impossible to debug for the end user, the
> > interfaces and file formats are not unified, each manufacturer
> > redesigns its own place and route algorithms... It is obviously a
> > stupid
> > waste of time and intellectual effort.
> >
> > So why not try to change this situation ? I suggest that the
> > opencores
> > project (and maybe other open hardware projects) officially
> > publishes an
> > open letter intended for FPGAs manufacturer (or individually mails
> > them), asking them for donating complete specifications of their
> > chip's
> > configuration bitstream. In return, opencores.org would start a
> > project of developping a GPL'd CAD tool which would target the
> > chips of
> > the manufacturer(s) answering this call.
> >
> > As it would have a modular design, such a tool could have different
> > frontends, the most important probably being for the AIRE IIR or
> > FIR
> > format (for integration with Savant and FreeHDL). One could add a
> > frontend
> > for the Jazz language netlist. Several backends for the different
> > supported FPGA architectures would be implemented. Of course, if we
> > obtained sponsoring from a FPGA manufacturer, I would volunteer for
> > this
> > project.
> >
> > But one could wonder why FPGA manufacturers would accept this deal.
> > Maybe
> > am I only dreaming... However the recent decisions of hardware
> > manufacturers (such as Creative Labs donating GPL'd driver for
> > their
> > SB Live) can give us some hope, though it is not exactly the same
> > context.
> > The Open Hardware movement is just at its beginning, but one could
> > imagine
> > (and it is probably the hope of everyone on this list) that it may
> > become
> > as important as the Open Software movement from an economical
> > vuepoint. It
> > could then look very attractive for a FPGA manufacturer to be the
> > "official" sponsor of this movement, by giving complete
> > specifications of
> > their chips, and being the main target for cores designed by this
> > community.
> >
> > I'm waiting for your thoughts or reactions :)
> >
> > Keep up the good work !
> >
> >       MoT
> >
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