[oc] Help: SDF Simulations

["RRK" <i_am_rrk@rediffmail.com>]

Hi All,

I am presently working as a PostGraduate Trainee for a Company in 
Hyderabad,India. I am into Xilinx FPGA-based Validation activity, 
for which I start with the verilog rtl of the design under test, 
Synthesize it and finally run P&R as well. We have a 
Design-specific Testing[Validation] Board over which we test this 
design. Running Post-Synthesis Simulation and SDF Simulation also 
forms a part of my duties here.

Now comming to my problem: I used Xilinx-ISE-3.1i's Design_Manager 
to generate the SDF file. I got a *.v file and a *.sdf file. I 
used the *.v file in my simulation environment. Can any one help 
me out with the procedure to run this simulation, please? I target 
my design to xcv2000e-6bg560 device.

Thank you

RRK


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