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Re: [oc] Error in DMA Core



The documentation seems to indicate that:

m_data_i = Master Interface Data Input
m_data_o =  Master Interface Data Output

These were previously hooked up to the wb_dma_wb_slv
module before.  And vice versa for the s_data_* signals.

The master instantiation previously looked like the following:

wb_dma_wb_mast	u0(
		.clk(		clk		),
		.rst(		rst		),
		.wb_data_i(	wbs_data_i	),
		.wb_data_o(	wbs_data_o	),
		.wb_addr_o(	wb_addr_o	),
		.wb_sel_o(	wb_sel_o	),
		.wb_we_o(	wb_we_o		),
		.wb_cyc_o(	wb_cyc_o	),
		.wb_stb_o(	wb_stb_o	),
		.wb_ack_i(	wb_ack_i	),
		.wb_err_i(	wb_err_i	),
		.wb_rty_i(	wb_rty_i	),
		.mast_go(	mast_go		),
		.mast_we(	mast_we		),
		.mast_adr(	mast_adr	),
		.mast_din(	mast_din	),
		.mast_dout(	mast_dout	),
		.mast_err(	mast_err	),
		.mast_drdy(	mast_drdy	),
		.mast_wait(	mast_wait	),
		.pt_sel(	pt_sel_i	),
		.mast_pt_in(	mast_pt_in	),
		.mast_pt_out(	mast_pt_out	)
		);

Here, we see that the wbs_data_* is sent into the same
module as mast_*.  If this is correct, it does not seem to 
agree with the documentation, since the slave data is 
combined with the master control (and vice versa for the
wb_dma_wb_slv interface)

Sorry if I'm understanding this wrong, it's not intuitive to me,
and even after re-reading the documentation, this is 
still contrary to what it seems to indicate.


----- Original Message ----- 
From: Rudolf Usselmann <rudi@a... > 
To: cores@o...  
Date: Sat, 27 Apr 2002 10:04:57 +0700 
Subject: Re: [oc] Error in DMA Core 

> 
> 
> 
> On Saturday 27 April 2002 00:17, you wrote: 
> > I think in the file wb_dma_wb_if.v, there is an error.  A 
> slight typo lead 
> > to the master data being connected to slave and vice versa. 
> > 
> > The lines 175/176 and 202/203 should be swapped. 
> > 
> > This lead to a completely non-functional controller.  This 
> should fix it. 
> > 
> > Has anyone noticed this before? 
> 
> No ! Read the documentation ! It clearly states which data bus is 
> going where. 
> 
> rudi 
> 
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