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Re: [oc] What kind of Algorithm level code can be synthesised?
Hello,
In theory, all algorithms are synthetizable in VHDL. You have all structures and operators of high level languages, like Pascal or C.
All is OK for simulation.
In practice, this is false for synthesis. The bad guy is the fitter, wich restricts many things. These limitations are documented in tool's docs.
One problem resides in multiplication implementation. Some tools don't implement a true multiplication in VHDL, only a left shift.
You must use a library multiplier, that is FPGA cells hungry and is not easy to use in behavioral architectures. You could try
Hadamard's transform wich only needs shift, add and substraction. All algorithms wich don't use true multiplications, integer or real
(and worst divisions) , are candidates for synthesis on suitable FPGA, with process in behavioral architectures.
Best regards,
J.M.
zeyaohan a écrit :
> Hello, everyone:
>
> I am puzzling at what kind of algorithm level hdl code can be synthesised and what kind of them can not?
> For example, designing FFT/IFFT processor, can i directly transfer C algorithm to hdl algorithm level description (behavior) and then let it be synthesised, or it can not be synthesised? For i think the Radix 4 and split Radix algorithm is complex and synthesis tools can not build specific memory and registers and control logic for them. How do you think about?
> And another example, designing FIR or IIR, i think whether i can only use formula to construct the algorithm level hdl code or need i describe detailed RTL level hdl code to be synthesised?
> And other examples, such as virtebi coder and decoder and reed-solomon coder and decoder.
> And such as DCT(discrete cosine transform), wavelet transform, and other digital signal processing algorithm?
>
> Best Regards!
> zeyaohan
> zeyaohan@263.net
>
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