Re: [oc] Re: Opencores Design Guidelines

["Jim Dempsey" <dempsey@northnet.net>]

I am a newbie at this so my comments may be of little value.
However, it is my observation that for a system where you have
say two time domains and a bridge device such as a Latch or FIFO
that each domain excepting for the bridge device could be simulated
independently using current tools. Then for the bridge device you
would want a variation of the simulation tool.

This variation may exist in the current tools or it may have to be created
for the expressed purpose of testing these time domain bridge like devices.
What the simulator would permit you to do is to set the clocks for
each time domain and additionally the simulator would vary a skew between
the time domains. This skew would sweep the full range of phase-edness
between the two time domains.

This procedure is somewhat like using a strobe light in a mechanical system
wherein you migrate the test point throughout the entire phase cycle by
turning a
pot that varies the strobe frequency. In this manner you could observe when
or if X point failures occur or not. Prior to simulation this kind of test
would
be done on the device with a multi trace scope (triggered) and a pot to vary
the clock rate(s). What you are looking for is a digital tool to simulate
this
type of setup.

Perhaps someone here can say "You can do this using XYZ Co's Dingdong 1000"

Jim Dempsey


----- Original Message -----
From: "llbutcher" <llbutcher@veriomail.com>
To: <cores@opencores.org>
Sent: Monday, November 12, 2001 3:10 AM
Subject: Re: [oc] Re: Opencores Design Guidelines


> Rudolf:
>
> I need to get a look at the text you identified as confusing.
>
> That's exactly my intent.
>
> 1) I am tired of gate-level simulation coming up all X's because
>     some RTL flip-flop in an always block had a setup or hold


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