Re: [oc] multi_second.vhd

["Yoshiaki Naruse" <sysworks@saitama-j.or.jp>]

Hi Jimmy

 Before talk about if this is the optimal design or not,
here's your result.

--- MTI simulation ---

vcom -reportprogress 300 -work work {[snap]multi_second.vhd}
# Model Technology ModelSim PE vcom 5.4b Compiler 2000.06
Jun  8 2000
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity multi_second
# -- Compiling architecture junk of multi_second
###### [snap]multi_second.vhd.vhd(29):    IF rst then
counter := 0;
# ERROR: [snap]multi_second.vhd(29): Type error in variable
rst. Needed type boolean.
# WARNING[10]: [snap]multi_second.vhd(29): Synthesis
Warning: Signal rst is read by the process
# but is NOT in the sensitivity list
###### {snap]multi_second.vhd(70): END JUNK;
# ERROR: [snap]multi_second.vhd(70): VHDL Compiler exiting

--- Leonardo synth results ---

Info, Working Directory is now [snap]
->set input_file_list { "[snap] /multi_second.vhd" }
 "[snap] multi_second.vhd"
->read { "[snap] /multi_second.vhd" }
-- Reading file e:\leospec\v20001a\data\standard.vhd for
unit standard
-- Loading package standard into library std
-- Reading vhdl file [snap] /multi_second.vhd into library
work
-- Reading file e:\leospec\v20001a\data\std_1164.vhd for
unit std_logic_1164
-- Loading package std_logic_1164 into library ieee
-- Searching for SYNOPSYS package std_logic_arith..
-- Reading file e:\leospec\v20001a\data\syn_arit.vhd for
unit std_logic_arith
-- Loading package std_logic_arith into library ieee
-- Loading entity multi_second into library work
"[snap] /multi_second.vhd",line 29: Error, type error in
expression.
Error in file [snap] /multi_second.vhd.
-- Error found in VHDL source

My suggestion is ...

 1 Do not use meaningless numbers itself in your code
directly.
   You can use *constants* or *generics* instead.
   This is just simulate to - C language - cases.
   It will give you much capability when used with proper
tools.

2 Do not use multiple-clocks without synchronization. This
is
  very basics if you R to implement your design into real
devices.
  You'd better not to ignore setup-hold time violation
problems
  which provides meta-stable states in your designs.


--------  Yoshiaki Naruse  --------------------

E-mail :   sysworks@saitama-j.or.jp
HomePage:  http://www.saitama-j.or.jp/~sysworks

----- Original Message -----
From: "Jimmy Hui" <pinesystems@home.com>
To: <cores@opencores.org>
Sent: Thursday, August 31, 2000 5:33 AM
Subject: [oc] multi_second.vhd


| Hi,
|
| I am quite new to vhdl.  I wrote a clock divider:
|
| 1.  Input - CLK in = 1.8432 Mhz
| 2.  Output - SECOND
| 3.  Output - 0.25 SECOND
|
| Can someone comment if this is the optimal design?
|
| Thanks,
|
| Jimmy