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Re: [openip] Re: Fwd: [[oc] Coding Conventions are up ]



Hi,

Nice to see your huge list of comments.
My comments are embedded.

>
>1. what about Port names

Ports have the same conventions as that of signals. The only difference 
is, if any module is getting input from external to the whole chip, then 
its name starts with "ext".

>2. what is the meaning of driving module is it the source of the
>signal, but what about multiple drivers of the same signal.

"Driving Module" of any signal means the module which generates the 
signal.

>3. 0,1 should not be used to show active high or low signals because
>they make confusion with the array indexes so I prefer 'n' and 'p'

I agree with this, P - Positive Logic (Active High), N - Negetive Logic 
(Active Low).

>4. I liked the signal names you proposed and I want to clarify it more
>xxxxAAAAnnnnnnnn where xxxx is four characters describing the driving
>module, component or process???.  AAAA is four characters describing
>the attributes of the signal.  nnnnnn is the name of the signal in
>lower case.

Apart from the fact that a signal name should contain all its historical 
details, it is necessary to have the signal names smaller. (Readability 
Increases). So lets have "xxx" for driving module. In AAAA I don't find 
any need to indicate the signal type. So I prefer "AAA". I prefer to 
give a relaxation on the size of  "nnnnnn" the thing which says what the 
signal is intended to do (function of signal). Because this is the 
important part of it to enhance readability.

>5. AAAA should be devided into groups where each character describe a
>signle atribute, 
[Bus,Clock,Wire,conTrol],[Global,Local],[Positive,Nega
>tive],[criticaL signal,],[if it can be Z stated],[Resolved ,Unresolved
>signal],[signal type should be one of the attributes,
>std_logivc,integer,bit,.....] may be we can adopt the windows naming
>convintions. it uses some kind of naming I mentioned here.

I don't think we need to have control as a part of  Bus, Wire, Clock, 
because the control signal will be genarated in the control unit and 
hence "xxx" will be "ctl" to indicate that it comes from control unit 
and it is a control signal.

As I said earlier if the function of signal is appropriately said, there 
is no need to explicitly specify the signal types. The implicit meaning 
should come from the function of signal.

>6. beh or behavior, str or structure. I agree that the architecture is
>related to the entity name so we can use the second convintion but we
>have to remmber that several architectures can be used to describe the
>same entity and all may be structural or so. Another issue is the
>synthesizable archs [syn], simulatable models[mod] and post
>synthesis[pst] archs types of library used after synthesis "vital
>[vtllb], technology specific library [techlb]" all should be 
considered.

In case of multiple architecture, the designer is given the liberty to 
concatenate the specific need for  that Arch with (behavioral, 
structural ...).

As far as a chip is considerd, simulatable-only modules are of no use. 
We will be interested in synthesizable yet simulatable models are the 
ones we are interested in. Still if we want to indicate whether it 
simulatable only or synthesizable only, we can specify that in the file 
name not inside the file.
We can name them as sim_alu.vhd, syn_alu.vhd .....
Regarding the libraries being used, yes it will be mentioned in the file 
header.

>7. Generics as constants all should be UPPER CASE

Yes I agree with generics being in upper case similar to constants.

>What about the Document style and its sections
>I suggest the following sections and to use the latex format
>
>1. comments
>2. Generics and constants
>3. Entity archs, configuration naming and packages
>4. signal naming
>5. variable naming
>6. processes & blocks naming
>7. procesdures and functions
>
>

More about configuration naming and packages, processes, blocks naming, 
procesdures & functions and also the documentation tips, I will come up 
in the updated conventions list soon.

Regards
Harish
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