head 1.2;
access;
symbols
initial:1.1.1.1 diogenes:1.1.1;
locks; strict;
comment @# @;
1.2
date 2008.02.04.17.56.19; author fellnhofer; state dead;
branches;
next 1.1;
commitid 10d747a751a24567;
1.1
date 2008.01.29.13.09.46; author fellnhofer; state Exp;
branches
1.1.1.1;
next ;
commitid e9847a74fd04567;
1.1.1.1
date 2008.01.29.13.09.46; author fellnhofer; state Exp;
branches;
next ;
commitid e9847a74fd04567;
desc
@@
1.2
log
@*** empty log message ***
@
text
@
Device Utilization Summary |
Logic Utilization | Used | Available | Utilization | Note(s) |
Total Number Slice Registers |
413 |
9,312 |
4% |
|
Number used as Flip Flops |
397 |
|
|
|
Number used as Latches |
16 |
|
|
|
Number of 4 input LUTs |
1,263 |
9,312 |
13% |
|
Logic Distribution | | | | |
Number of occupied Slices |
784 |
4,656 |
16% |
|
Number of Slices containing only related logic |
784 |
784 |
100% |
|
Number of Slices containing unrelated logic |
0 |
784 |
0% |
|
Total Number of 4 input LUTs |
1,449 |
9,312 |
15% |
|
Number used as logic |
1,263 |
|
|
|
Number used as a route-thru |
57 |
|
|
|
Number used for Dual Port RAMs |
128 |
|
|
|
Number used as Shift registers |
1 |
|
|
|
Number of bonded IOBs |
35 |
232 |
15% |
|
IOB Flip Flops |
21 |
|
|
|
Number of Block RAMs |
7 |
20 |
35% |
|
Number of GCLKs |
1 |
24 |
4% |
|
Total equivalent gate count for design |
479,243 |
|
|
|
Additional JTAG gate count for IOBs |
1,680 |
|
|
|